Field programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence “field-programmable”. FPGAs are integrated circuits that can be tailored to suit a particular task like mining bitcoins, after their manufacturing thus creating ASIC.

What is FPGA?

The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of a portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.

FPGAs contain programmable logic components called “logic blocks”, and a hierarchy of reconfigurable interconnects that allow the blocks to be “wired together” somewhat like many logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.

FPGA Architecture

A FPGA from Altera

The FPGA includes three main programmable element:

  • non-commuted programmable logic blocks (PLBs);
  • I / o units (I / o units));
  • internal communication.

Lbf are the functional elements for constructing user’s logic. BVV provide communication between the contacts of the body and the internal signal lines. Programmable internal communications resources control the ways of connecting the inputs and outputs of PLBs and I / o units (I / o units) to the respective networks. All trace channels have the same width (the same number of conductors). Most I / o units (I / o units) are either in the same row (height) or in the same column (width) of the valve array.

The logical unit (PLB) of a classical PMPP consists of a truth table (see discussion) (eng. lookup table, LUT) on four inputs and one trigger (see figure below). In recent years manufacturers have begun converting to a truth table with large number of inputs, which allows you to use fewer logic blocks for typical applications.


A typical logical block

The logical unit (PLB) has a truth table with four inputs and a clock input. The unit output is only one-register or non-register output truth table. Since the synchronization signals in commercial AVMS (and often other signals parallelized by a large number of inputs — high-fanout signals) are traced in a special way by special tracing circuits, the management of these signals is done separately.

For the following example architecture, the location of the logical block contacts is shown below.

Location of logical block contacts

The inputs are located on separate sides of the logical unit; the output pin can be traced in two channels: either to the right of the unit or to the bottom. The output pins of each logical unit can be connected to trace segments in adjacent channels. Similarly, the I / o unit (pad) contact area can be connected to a trace element in any adjacent channel. For example, the upper contact area of the chip can be connected to any of the W conductors (where W is the width of the channel) in a horizontal channel located directly below it.

As a rule, the AVM trace is not segmented, that is, each conductor segment connects only one logical block with the switch block. Due to the diffraction of the programmable switches in the switch trace turns out to be longer. In order to increase the speed of in-system connections, longer trace connections are used between logical blocks in some IMPM architectures.

Switch blocks are created at the intersection of vertical and horizontal channels. With this architecture, there are three programmable switches for each conductor in the switch box that allow it to connect to three other conductors in adjacent channel segments. The switch model or topology used in this architecture is the planar or domain topology of the switch units. In this topology, a guide to highway 1 is only connected to the conductor tracks of the number 1 in the adjacent channels, the guide route No. 2 is connected only to the conductors of the track number 2 and so on. The figure below shows the connections in the switch box.

The topology of the switch block

Modern FPGA families expand the opportunities listed above and include built-in functionality at a high level. Due to the presence of these common functions in the silicon crystal, it is possible to reduce the area of the crystal, in addition to this scheme, these functions will work faster than when they are implemented on the basis of primitives. Examples of such functions are multiplexers, digital signal processing units, built-in processors, fast I / o logic, and built-in memory.

PMTCT is also widely used for suitability testing systems, including pre-and post-silicon suitability testing, as well as in the development of programs for embedded systems. This allows manufacturers of integrated circuits to test the performance of their devices before manufacturing them at the factory, reducing the time of entry into the market.

Different FPGAs

Product Hash rate
Avnet Spartan-6 LX150T Development Kit 100 0.10 995
Bitcoin Dominator X5000 100 440
BitForce SHA256 Single 832 10.4 1.38 80 599
Butterflylabs Mini Rig 25,200 20.16 1.64 1,250 15,295
Digilent Nexys 2 500K 5 0.03 149
Icarus 380 19.79 0.66 19.2 569
KnCMiner Mars 6,000  ??? 2.15  ??? 2,795
Lancelot 400 26 350
ModMiner Quad 800 20 0.75 40 1,069
Terasic DE2-115 80 0.13 595
X6500 FPGA Miner 400 23.25 0.72 17.2 550
ZTEX USB-FPGA Module 1.15b 90 0.27 325
ZTEX USB-FPGA Module 1.15x 215 0.52 406
ZTEX USB-FPGA Module 1.15y 860 0.65 1,304

Product Algorithm
Hash rate
Xilinx VCU1525 0xToken (SHA3) 18 350W 4000
SQRL BCU1525 0xToken (SHA3) 18 350W 3450
TUL BTU9P 0xToken (SHA3) 18 350W 3599
Hashaltcoin F1 Blackminer 0xToken (SHA3) 21.6 600W 1900
Hashaltcoin F1 Mini Blackminer 0xToken (SHA3) 1.95 50W 179
Hashaltcoin F1+ Blackminer 0xToken (SHA3) 35.20 1020W 3100


The Application Specific Integrated Circuit is a unique type of IC that is designed with a certain purpose in mind. This type of ICs are very common in most hardware nowadays since building with standard IC components would lead to big and bulky circuits. An FPGA (Field Programmable Gate Array) is also a type of IC, but it does not have the programming built into it during the production. As the name implies, the IC can be programmed by the user as long as he has the right tools and proper knowledge.

An ASIC can no longer be altered after it gets out of the production line. That is why the designers need to be totally sure of their design, especially when making large quantities of the same ASIC. The programmable nature of an FPGA allows the manufacturers to correct mistakes and to even send out patches or updates after the product has been bought. Manufacturers also take advantage of this by creating their prototypes in an FPGA so that it can be thoroughly tested and revised in the real world before actually sending out the design to the IC foundry for ASIC production.

ASICs have a great advantage in terms of recurring costs as very little material is wasted due to the fixed number of transistors in the design. With an FPGA, a certain number of transistor elements are always wasted as these packages are standard. This means that the cost of an FPGA is often higher than that of a comparable ASIC. Although the recurring cost of an ASIC is quite low, its non-recurring cost is relatively high and often reaching into the millions. Since it is non-recurring though, its value per IC decreases with increased volume. If you analyze the cost of production in relation to the volume, you would find that as you go lower in production numbers, using FPGA actually becomes cheaper than using ASICs.

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